New Fault Simulator for Large Synchronous Sequential Circuits

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. 1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. 2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. 3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. 4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while agating packets, equivalent stem faults are also inserted the packets and propagated as well. A memory sharing technique i s used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.l) for large synchronous sequential benchmark circuits. Fault simulation is the process of estimating the effectiveness of a sequence of test vectors by deter-mining which faults in a given set will be detected by the test vectors. A fault simulator is usually embedded in an automatic test pattern generation (ATPG) system for finding other faults, which are detected by the same test after a test sequence is generated for one target fault by a test generator. For each test pattern, the good machine and the faulty machines are simulated. If the output responses of a faulty machine differ from those of the good machine, then the corresponding fault is said to have been detected and the fault is removed from simulation by the subsequent test patterns. In this manner, the number of faults which need to be processed by a test generator can be dramatically reduced. Hence, a fault simulator not only grades the quality of a test sequence but also speeds up the test generation process. As VLSI technologies are rapidly developing, circuits can contain a great deal of faults that need to be detected. This has greatly challenged the testing engineers, who have consequently developed several efficient fault simulators to deal with the problem [1]-[5]. A simplified single stuck-at fault model, which assumes that a circuit can contain at most one defect and the defect can be represented as a single line staying fixed at a high voltage (a stuck-at-1 fault) or staying at a low voltage (a stuck-at-0 fault), has been shown to be a good approximation of actual manufacturing defects. Therefore, most of the present fault simulators are based on the single stuck-at fault model. In this paper, only the single stuck-at faults are considered. 11. Background A. Definitions and terms A synchronous sequential circuit can be turned into a combinational one when all its flip-flops (FFs) are removed from the circuit. The outputs of the FFs in the combinational circuit are called pseudo-primary inputs (PPIs) and the inputs of FFs are called pseudo-primary outputs (PPOs). Two major differences exist between a combinational circuit and a sequential one from the viewpoint of fault simulation. Firstly, combinational circuit fault simulators are two-valued simulators, while sequential ones are three-valued, 0, 1, and x (unknown), simulators. This difference is caused by the uncertainty of the initial value of each FF. Secondly, the faulty effect of a fault can only originate at its faulty site in the combinational circuit, while in the sequential one, the faulty effect can originate at its faulty site, as well as at the PPIs, since the FFs can store the effects of faults. Because nf these differences, developing a sequential circuit fault simulator is much more difficult than developing a combinational one. Consequently, some efficient combinational circuit fault simulation methods cannot be extended to sequential ones [6]-[8]. A circuit consists of many fanout free regions (FTRs). The output of each FFR can be a stem, a PPO, or a primary output (PO). For simplicity, POs and PFQs are considered as stems in this paper. We use WR(s) to denote the FFR whose output is s. B. Previous work B.1 Parallel fault simulation The parallel fault simulation algorithm 191 takes advantage of the word level parallelism of a computer, to simulate 32 (for a 32-bit computer) circuits per pass. Each pass consists of 1 good (fault-free) circuit and 31 faulty circuits. The parallel algorithm suffers from the problem of the repetition of the good circuit simulation in every pass and also from its inability to drop detected faults, so that after a fault is detected, one bit space is wasted for the remainder of that pass of the simulation. These problems have been solved by a parallel fault simulator, called PROOFS [2], in which only the active undetected faults are simulated in parallel, 32 faults in a pass. Since then, some new techniques [3]-[5] have been developed to reduce the number of active faults, so as to reduce the number of simulation passes. Consequently, the fault simulation time has been reduced. However, when the 1 OA.4.1 0-7803-2440-4/94/ $4.00 @ 1994 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on March 16, 2009 at 05:40 from IEEE Xplore. Restrictions apply. circuit under fault simulation is very large, two serious problems arise. 1) There is a need to save the faulty status of the faults, whose effects have been propagated to PPOs, and then restore them for parallel simulation under the application of the next test pattern. When there are a large number of such faults activated during fault simulation, the storing and restoring of faulty status becomes a big overhead. 2) Since each simulation pass simulates 32 faults in parallel, many passes are needed for a circuit with a lot of multiple event faults under a given test set. Consequently, many gates are simulated many times for each test pattern. In our fault simulator, these problems have been overcome since all the multiple event faults are simulated simultaneously. B.2 Deductive fault simulation The deductive fault simulation simulates the good circuit and deduces the behavior of all faulty circuits [lo]. The advantage of this is that the number of events being simulated is low, since only a one-pass simulation is needed for each test pattern. However, since each active fault has a fault list to store the faults whose faulty effects propagate to it, the memory usage is enormous when there are a lot of faults under fault simulation. Also, maintaining the fault lists takes up a great deal of CPU time. €3.3 Critical path tracing A combinational circuit fault simulator based on the concepts of line criticality and iine sensitivity [ l 11 has been developed and called CRIFT [ 121. The major advantage of CRIPT is that it deals with faults only implicitly, i.e., without doing faulty effect propagation as done in deductive fault simulation. Therefore, fault collapsing, fault insertion, and fault dropping are not necessary. Although CRIPT is efficient in speed, it is not an exact fault simulator since some faults that can be detected by multiple path sensitization are not identified as detected. 111. Proposed fault simulator In this section, we describe the algorithm of our fault simulation which takes the advantages of the above methods. The basic idea is to simultaneously simulate the faults that have multiple effects under the application of the current test pattern. These faults include equivalent stem faults and multiple event faults [3]. We call them multiple effect faults. The outline of our fault simulator is shown in Fig. 1. The major operations in it are described in the followings.